1. Field of the Invention
The present invention relates to a charge pump circuit, and more particularly to a charge pump circuit that effectively prevents an occurrence of a body effect of metal oxide semiconductor field-effect transistors (MOSFETs).
2. Description of Related Art
In order to lower power consumption, an operating voltage for integrated circuits (ICs) is modified to a lower level. For example, the normal operating voltage for the ICs has been changed from the early 5 volts to the present 3.3 volts, and sometimes even lower than 2 volts. Although a lower operating voltage is beneficial for power consumption reduction, some particular applications requiring a high operating voltage still should be concerned. In particular, while erasing data stored in a flash memory, a large negative voltage, usually −9 or −10 volts, is necessary and supplied by a charge pump circuit.
A conventional negative voltage charge pump circuit is disclosed in FIG. 7. The negative voltage charge pump comprises eight boosting stages (only four stages are shown) and an output stage. Each boosting stage has a P-channel type main pass transistor (301)-(301) connected to an adjacent transistor in series, a P-channel type pre-charge transistor (331)-(334) and two capacitors (311)-(314) and (321)-(324). All the boosting stages are driven by four clock signals (CLK1–CLK4).
The clock signals CLK1 and CLK4 firstly remain at a low level to respectively activate the main pass transistor (301) in the first boosting stage and the pre-charge transistor (332) in the second boosting stage. Then, the clock signal CLK1 turns to a high level to deactivate the main pass transistor (301) in the first boosting stage. Simultaneously, the clock signal CLK2 becomes a low level signal thus conducting the pre-charge transistor (331) and resulting in a discharge of the capacitor (311). The capacitor (321) subsequently has a −VCC potential and the main pass transistor (301) is deactivated. The clock signal CLK2 still continuously charges the capacitor (312) until the CLK4 signal becomes a high level signal to deactivate the pre-charge transistor (332).
Since the main pass transistor (302) of the second boosting stage has been charged to a negative potential prior to the activating of the pre-charge transistor (332), a voltage level at the gate of the main pass transistor (302) is lower than that of its source. Therefore, when the main pass transistor (302) is activated, the capacitor (322) can be quickly charged to −2×VCC. Using the foregoing technique, the input voltage can be gradually boosted by the boosting stages and a negative voltage is finally derived Vout=−((N×VCC)−Vt.
The foregoing circuit operation is also suitable for a positive voltage charge circuit as shown in FIG. 4 of Taiwan Patent no. 477977, wherein the N-channel type transistors are employed to replace the P-channel transistors of FIG. 3 and the clock signals are also accordingly modified.
As discussed above, the charge pump circuits have been widely used. However, some deficiencies of the conventional charge pump circuits still exist.
As well known in the art, a parasitic bipolar transistor exists between an N-type well region and a P-type well region of an N-channel type MOSFET. When the parasitical bipolar transistor is turned on, a voltage across the body and the source of the parasitical bipolar transistor itself is not zero, which will affect the threshold voltage of the N-channel type MOSFET the so-called body effect. Therefore, when a charge pump circuit utilizes the N-channel type MOSFETs as the main pass transistors, the N-channel type MOSFETs can not be quickly activated thus causing an undesired delay result in the flowing of the charge current through the boosting stages. The efficiency of the charge pump circuit will accordingly be negatively influenced.
Therefore, the invention provides a novel charge pump circuit to mitigate or obviate the aforementioned problem.